Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a storage node in a semiconductor device.
As the integration density of semiconductor devices increases, the size of the semiconductor devices is being reduced. Thus, an important issue is to somehow ensure an adequate capacity for a capacitor. In particular, in the case of a dynamic random access memory (DRAM) consisting of a transistor and a capacitor, it is very important to increase a capacitance while reducing an area of the capacitor. In order to increase the capacity of a capacitor, various capacitor materials and various capacitor fabricating methods have been developed. For example, a method which increases a height of a capacitor can improve a capacitance by increasing an area of a capacitor, but suffers a physical limitation in increasing the height of the capacitor due to a deficient process margin of a photo process and an etching process.
One of methods which increase an area of a capacitor in order to ensure an adequate capacitance for a capacitor is to use a meta stable poly silicon (MPS) process. An MPS process is applied to a concave structure. A method for increasing a capacitance of a capacitor by using an MPS process can increase an area of a capacitor.
However, as the integration density of semiconductor devices has recently increased, the semiconductor devices shrinks in size and the capacitor also shrinks in size. A space margin in which an MPS process can be performed is not sufficiently ensured, causing a bridge at an upper portion of the capacitor. Furthermore, the concave structure has a limit in increasing a capacitance of a capacitor because only one surface of the capacitor is used.